Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process. View Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with ...

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...